Chipmakers proceed to claw for each spare nanometer to proceed cutting down circuits, however a expertise involving issues which might be a lot larger—lots of or hundreds of nanometers throughout—could possibly be simply as important over the subsequent 5 years.
Referred to as hybrid bonding, that expertise stacks two or extra chips atop each other in the identical package deal. That permits chipmakers to extend the variety of transistors of their processors and recollections regardless of a basic slowdown within the shrinking of transistors, which as soon as drove Moore’s Regulation. On the
IEEE Electronic Components and Technology Conference (ECTC) this previous Could in Denver, analysis teams from all over the world unveiled quite a lot of hard-fought enhancements to the expertise, with a couple of exhibiting outcomes that would result in a file density of connections between 3D stacked chips: some 7 million hyperlinks per sq. millimeter of silicon.
All these connections are wanted due to the brand new nature of progress in
semiconductors, Intel’s Yi Shi advised engineers at ECTC. Moore’s Law is now ruled by an idea known as system expertise co-optimization, or STCO, whereby a chip’s features, corresponding to cache reminiscence, enter/output, and logic, are fabricated individually utilizing one of the best manufacturing expertise for every. Hybrid bonding and different superior packaging tech can then be used to assemble these subsystems in order that they work each bit in addition to a single piece of silicon. However that may occur solely when there’s a excessive density of connections that may shuttle bits between the separate items of silicon with little delay or vitality consumption.
Out of all of the advanced-packaging applied sciences, hybrid bonding offers the very best density of vertical connections. Consequently, it’s the quickest rising phase of the advanced-packaging business, says
Gabriella Pereira, expertise and market analyst at Yole Group. The general market is ready to greater than triple to US $38 billion by 2029, in accordance with Yole, which initiatives that hybrid bonding will make up about half the market by then, though right now it’s only a small portion.
In hybrid bonding, copper pads are constructed on the highest face of every chip. The copper is surrounded by insulation, normally silicon oxide, and the pads themselves are barely recessed from the floor of the insulation. After the oxide is chemically modified, the 2 chips are then pressed collectively face-to-face, in order that the recessed pads on every align. This sandwich is then slowly heated, inflicting the copper to increase throughout the hole and fuse, connecting the 2 chips.
Making Hybrid Bonding Higher
- Hybrid bonding begins with two wafers or a chip and a wafer going through one another. The mating surfaces are lined in oxide insulation and barely recessed copper pads related to the chips’ interconnect layers.
- The wafers are pressed collectively to type an preliminary bond between the oxides.
- The stacked wafers are then heated slowly, strongly linking the oxides and increasing the copper to type {an electrical} connection.
- To type safer bonds, engineers are flattening the previous few nanometers of oxide. Even slight bulges or warping can break dense connections.
- The copper should be recessed from the floor of the oxide simply the correct quantity. An excessive amount of and it’ll fail to type a connection. Too little and it’ll push the wafers aside. Researchers are engaged on methods to regulate the extent of copper right down to single atomic layers.
- The preliminary hyperlinks between the wafers are weak hydrogen bonds. After annealing, the hyperlinks are robust covalent bonds [below]. Researchers anticipate that utilizing several types of surfaces, corresponding to silicon carbonitride, which has extra areas to type chemical bonds, will result in stronger hyperlinks between the wafers.
- The ultimate step in hybrid bonding can take hours and require excessive temperatures. Researchers hope to decrease the temperature and shorten the method time.
- Though the copper from each wafers presses collectively to type {an electrical} connection, the metallic’s grain boundaries usually don’t cross from one aspect to the opposite. Researchers are attempting to trigger massive single grains of copper to type throughout the boundary to enhance conductance and stability.
Hybrid bonding can both connect particular person chips of 1 measurement to a wafer stuffed with chips of a bigger measurement or bond two full wafers of chips of the identical measurement. Thanks partially to its use in digital camera chips, the latter course of is extra mature than the previous, Pereira says. For instance, engineers on the European microelectronics-research institute
Imec have created among the most dense wafer-on-wafer bonds ever, with a bond-to-bond distance (or pitch) of simply 400 nanometers. However Imec managed solely a 2-micrometer pitch for chip-on-wafer bonding.
The latter is a big enchancment over the superior 3D chips in manufacturing right now, which have connections about 9 μm aside. And it’s a good larger leap over the predecessor expertise: “microbumps” of solder, which have pitches within the tens of micrometers.
“With the gear accessible, it’s simpler to align wafer to wafer than chip to wafer. Most processes for microelectronics are made for [full] wafers,” says
Jean-Charles Souriau, scientific chief in integration and packaging on the French analysis group CEA Leti. Nevertheless it’s chip-on-wafer (or die-to-wafer) that’s making a splash in high-end processors corresponding to these from AMD, the place the approach is used to assemble compute cores and cache reminiscence in its superior CPUs and AI accelerators.
In pushing for tighter and tighter pitches for each eventualities, researchers are targeted on making surfaces flatter, getting certain wafers to stay collectively higher, and slicing the time and complexity of the entire course of. Getting it proper might revolutionize how chips are designed.
WoW, These Are Some Tight Pitches
The latest wafer-on-wafer (WoW) analysis that achieved the tightest pitches—from 360 nm to 500 nm—concerned lots of effort on one factor: flatness. To bond two wafers along with 100-nm-level accuracy, the entire wafer needs to be practically completely flat. If it’s bowed or warped to the slightest diploma, entire sections gained’t join.
Flattening wafers is the job of a course of known as chemical mechanical planarization, or CMP. It’s important to chipmaking usually, particularly for producing the layers of interconnects above the
transistors.
“CMP is a key parameter now we have to regulate for hybrid bonding,” says Souriau. The outcomes offered at ECTC present CMP being taken to a different degree, not simply flattening throughout the wafer however decreasing mere nanometers of roundness on the insulation between the copper pads to make sure higher connections.
“It’s tough to say what the restrict will probably be. Issues are transferring very quick.” —Jean-Charles Souriau, CEA Leti
Different researchers targeted on guaranteeing these flattened elements stick collectively strongly sufficient. They did so by experimenting with completely different floor supplies corresponding to silicon carbonitride as a substitute of silicon oxide and by utilizing completely different schemes to chemically activate the floor. Initially, when wafers or dies are pressed collectively, they’re held in place with comparatively weak hydrogen bonds, and the priority is whether or not all the pieces will keep in place throughout additional processing steps. After attachment, wafers and chips are then heated slowly, in a course of known as annealing, to type stronger chemical bonds. Simply how robust these bonds are—and even determine that out—was the topic of a lot of the analysis offered at ECTC.
A part of that closing bond power comes from the copper connections. The annealing step expands the copper throughout the hole to type a conductive bridge. Controlling the scale of that hole is vital, explains Samsung’s
Seung Ho Hahn. Too little growth, and the copper gained’t fuse. An excessive amount of, and the wafers will probably be pushed aside. It’s a matter of nanometers, and Hahn reported analysis on a brand new chemical course of that he hopes to make use of to get it good by etching away the copper a single atomic layer at a time.
The standard of the connection counts, too. The metals in chip interconnects aren’t a single crystal; as a substitute they’re made up of many grains, crystals oriented in several instructions. Even after the copper expands, the metallic’s grain boundaries usually don’t cross from one aspect to a different. Such a crossing ought to cut back a connection’s electrical resistance and increase its reliability. Researchers at Tohoku College in Japan reported a brand new metallurgical scheme that would lastly generate massive, single grains of copper that cross the boundary. “It is a drastic change,” says
Takafumi Fukushima, an affiliate professor at Tohoku. “We are actually analyzing what underlies it.”
Different experiments mentioned at ECTC targeted on streamlining the bonding course of. A number of sought to scale back the annealing temperature wanted to type bonds—sometimes round 300 °C—as to attenuate any danger of injury to the chips from the extended heating. Researchers from
Applied Materials offered progress on a way to radically cut back the time wanted for annealing—from hours to simply 5 minutes.
CoWs That Are Excellent within the Subject
Imec used plasma etching to cube up chips and provides them chamfered corners. The approach relieves mechanical stress that would intervene with bonding.Imec
Chip-on-wafer (CoW) hybrid bonding is extra helpful to makers of superior CPUs and GPUs in the mean time: It permits chipmakers to stack
chiplets of various sizes and to check every chip earlier than it’s certain to a different, guaranteeing that they aren’t dooming an costly CPU with a single flawed half.
However CoW comes with the entire difficulties of WoW and fewer of the choices to alleviate them. For instance, CMP is designed to flatten wafers, not particular person dies. As soon as dies have been lower from their supply wafer and examined, there’s much less that may be achieved to enhance their readiness for bonding.
However, researchers at
Intel reported CoW hybrid bonds with a 3-μm pitch, and, as talked about, a workforce at Imec managed 2 μm, largely by making the transferred dies very flat whereas they have been nonetheless connected to the wafer and protecting them additional clear all through the method. Each teams used plasma etching to cube up the dies as a substitute of the standard technique, which makes use of a specialised blade. Not like a blade, plasma etching doesn’t result in chipping on the edges, which creates particles that would intervene with connections. It additionally allowed the Imec group to form the die, making chamfered corners that relieve mechanical stress that would break connections.
CoW hybrid bonding goes to be vital to the way forward for high-bandwidth reminiscence (HBM), in accordance with a number of researchers at ECTC. HBM is a stack of DRAM dies—at the moment 8 to 12 dies excessive—atop a control-logic chip. Usually positioned throughout the identical package deal as high-end
GPUs, HBM is crucial to dealing with the tsunami of knowledge wanted to run large language models like ChatGPT. As we speak, HBM dies are stacked utilizing microbump expertise, so there are tiny balls of solder surrounded by an natural filler between every layer.
However with AI pushing reminiscence demand even greater, DRAM makers need to stack 20 layers or extra in HBM chips. The amount that microbumps take up signifies that these stacks will quickly be too tall to suit correctly within the package deal with GPUs. Hybrid bonding would shrink the peak of HBMs and likewise make it simpler to take away extra warmth from the package deal, as a result of there could be much less thermal resistance between its layers.
“I feel it’s attainable to make a more-than-20-layer stack utilizing this expertise.” —Hyeonmin Lee, Samsung
At ECTC, Samsung engineers confirmed that hybrid bonding might yield a 16-layer HBM stack. “I feel it’s attainable to make a more-than-20-layer stack utilizing this expertise,” says
Hyeonmin Lee, a senior engineer at Samsung. Different new CoW expertise might additionally assist convey hybrid bonding to high-bandwidth reminiscence. Researchers at CEA Leti are exploring what’s generally known as self-alignment expertise, says Souriau. That might assist guarantee good CoW connections utilizing simply chemical processes. Some elements of every floor could be made hydrophobic and a few hydrophilic, leading to surfaces that will slide into place mechanically.
At ECTC, researchers from Tohoku College and Yamaha Robotics reported work on the same scheme, utilizing the floor rigidity of water to align 5-μm pads on experimental DRAM chips with higher than 50-nm accuracy.
The Bounds of Hybrid Bonding
Researchers will nearly definitely preserve decreasing the pitch of hybrid-bonding connections. A 200-nm WoW pitch isn’t just attainable however fascinating,
Han-Jong Chia, a venture supervisor for pathfinding programs at Taiwan Semiconductor Manufacturing Co. , advised engineers at ECTC. Inside two years, TSMC plans to introduce a expertise known as backside power delivery. (Intel plans the identical for the tip of this yr.) That’s a expertise that places the chip’s chunky power-delivery interconnects under the floor of the silicon as a substitute of above it. With these energy conduits out of the way in which, the uppermost ranges can join higher to smaller hybrid-bonding bond pads, TSMC researchers calculate. Bottom energy supply with 200-nm bond pads would lower down the capacitance of 3D connections a lot {that a} measure of vitality effectivity and sign pace could be as a lot as eight occasions higher than what may be achieved with 400-nm bond pads.
Chip-on-wafer hybrid bonding is extra helpful than wafer-on-wafer bonding, in that it may place dies of 1 measurement onto a wafer of bigger dies. Nevertheless, the density of connections that may be achieved is decrease than for wafer-on-wafer bonding.Imec
Sooner or later sooner or later, if bond pitches slim even additional, Chia suggests, it would develop into sensible to “fold” blocks of circuitry so they’re constructed throughout two wafers. That method a few of what are actually lengthy connections throughout the block may be capable of take a vertical shortcut, doubtlessly dashing computations and decreasing energy consumption.
And hybrid bonding will not be restricted to silicon. “As we speak there may be lots of growth in silicon-to-silicon wafers, however we’re additionally seeking to do hybrid bonding between gallium nitride and silicon wafers and glass wafers…all the pieces on all the pieces,” says CEA Leti’s Souriau. His group even offered analysis on hybrid bonding for quantum-computing chips, which includes aligning and bonding superconducting niobium as a substitute of copper.
“It’s tough to say what the restrict will probably be,” Souriau says. “Issues are transferring very quick.”
This text was up to date on 11 August 2024.
This text seems within the September 2024 print difficulty.
